1. Field of the Invention
The present disclosure relates to integrating imaging pixels, and more particularly to a layout for routing common signals to integrating imaging pixels.
2. Description of Related Art
Many conventional layouts for arrays of integrating imaging pixels include multiple signal lines for transmitting common signals to adjacent imaging pixels. The imaging pixels can be arranged on one or more metal layers. The imaging pixels can have integrating capacitors that are metal-insulator-metal (MiM) capacitors that compete with the signal lines for allocation of the metal layers. When the well capacity of a MiM capacitor disposed in an imaging pixel is increased, the dynamic range performance of the imaging pixel is increased. The well capacity of the MiM capacitor depends upon the size of the metal layers allocated to the MiM capacitor. However, the signal lines compete with the MiM capacitors for allocation of the metal layers. As the number of signal lines increases, the area of the metal layers that can be allocated to the MiM capacitors is reduced, and the dynamic range performance of the integrating pixels can be reduced.
Such conventional methods and systems have generally been considered satisfactory for their intended purpose. However, there is still a need in the art for improved layouts of integrating imaging pixel cells. The present disclosure provides a solution for these problems.